The present invention relates to a semiconductor device including a repetitive pattern and, more specifically, to a dynamic semiconductor device (DRAM) including a repetitive pattern such as a word-line driving circuit.
This application is based on a Japanese Patent Application No. 10-369282 filed Oct. 25, 1998, the contents of which is incorporated herein by reference.
Recently DRAMs have been decreased greatly in size of element structure. In particular, word lines for selecting memory cells arranged in a memory cell array are formed under design rules. The width of one word line and the interval between adjacent word lines are decreased further. Moreover, a word-line driving circuit for selectively driving such a word line needs to be disposed in a narrow area. Some prior art methods have been therefore developed.
FIGS. 1 to 3 each illustrate a relationship between word lines and word-line driving circuits as one of the prior art methods. In FIG. 1, word-line driving circuits 210 connected to their respective word lines WL0, WL1, . . . , are arranged on one side of a memory cell array (MCA) 211. In the actual pattern layout, a word-line driving circuit is difficult to dispose between fine word lines. It is thus thought that the word-line driving circuits 210 are arranged on either side of the memory cell array 211 as shown in FIGS. 2 and 3. FIG. 2 is directed to a method of driving adjacent word lines alternately one by one by means of the word-line driving circuits 210 arranged on both sides of the memory cell array 211. FIG. 3 is directed to a method of driving adjacent word lines alternately two by two by means of the word-line driving circuits 210 arranged on both sides of the memory cell array 211. Of the above three methods shown in FIGS. 1 to 3, an appropriate one to be processed the most easily is selected according to a process technique such as lithography and etching.
When the word-line driving circuits are arranged as shown in FIGS. 1 to 3, a plurality of word-line driving circuits corresponding to a plurality of word lines are combined into one repetitive unit. A plurality of such repetitive units are arranged. In a normal DRAM, word lines are selected by decoding a low-order n bit (n.gtoreq.1) input address. One repetitive unit therefore coincides with 2.sup.n word lines. Assuming that an input address is two bits of A1 and A0, the word-line driving circuits connected to four word lines corresponding to logical values (0, 0), (0, 1), (1, 0) and (1, 1) of (A1, A0), constitute one repetitive unit.
FIGS. 4 and 5 show a circuit arrangement of the above repetitive unit and a layout of wires. Referring to these figures, word-line driving circuits 210 (referred to as word-line decoders hereinafter) are each constituted of a NAND circuit 210a and an inverter circuit 210b. A first metal wiring layer M1 is connected to an input terminal of the NAND circuit 210a. Address signals (low-order bits of an input address) A0, /A0, A1 and /A1 (/ indicates an inverted signal) are supplied to a plurality of second metal wiring layers M2 formed above the first metal wiring layer M1. These layers M1 and M2 are connected by a contact CT located in a desired position. The high-order bit of the input address is supplied to the input terminal of the NAND circuit 210a, but its description is omitted for simplification.